1. Field of the Invention
The present invention relates to a semiconductor device, and particularly relates to a semiconductor device including a static-type semiconductor memory.
2. Description of the Background Art
In a low-power-consumption semiconductor device, a standby mode (sleep mode) in which power supply is shut off may be provided. In the standby mode, a power voltage is supplied only to some circuits necessary for holding data, such as a memory cell of an SRAM (Static Random Access Memory).
In the SRAM described in Japanese Patent Laying-Open No. 11-219589, for example, supply of a power supply voltage to the circuits other than a memory cell and a word line potential clamping circuit is shut off during a sleep period in which data is held. The word line potential clamping circuit clamps the word line to a non-selection level during the sleep period, so as to prevent instability in word line potential and the resultant data corruption in the memory cell.
Japanese Patent Laying-Open No. 2006-252718 discloses a semiconductor storage device that can operate with much lower power consumption in a standby mode. In the semiconductor storage device, an output node of each word line driver is brought into a high impedance state so as not to allow a gate leak current to flow through each word line driver in the standby mode. Further, each word line is provided with a half latch circuit for clamping the word line to a non-activated level.
Japanese Patent Laying-Open No. 07-244982 discloses a technique for deterring a current that transiently flows to a word line, when a semiconductor memory device is brought into an inactive state (i.e. in a standby mode). In the conventional technique, there is provided setting means for setting an output of a multi-input logic gate (row decoder) to a logic level at which a signal indicating a non-selection state is outputted to a word line. Further, there is provided shut-off means for shutting off a flow-through current that flows from a power supply potential to a ground potential in the multi-input logic gate.
The conventional technique described in Japanese Patent Laying-Open No. 07-254274 is for providing a word line noise killer circuit array between a memory cell array and a word line drive circuit array. The word line noise killer circuit suppresses variations in potential level of an output node of a row decoder.
When an operational mode of the semiconductor device is shifted from a normal mode to a standby mode, or returns to the normal mode from the standby mode, a noise may be generated in association with a falling edge or a rising edge of the power supply voltage. When the generated noise flows from the word line driver to the word line, an access transistor of the memory cell may be brought into conduction to cause erroneous write to the memory cell. The conventional techniques described above cannot sufficiently prevent the erroneous write to the memory cell, caused by such a noise.